This invention relates to methods of fabricating power devices and the resulting devices, and more particularly to silicon carbide power devices and methods of fabricating silicon carbide power devices.
Power devices are widely used to carry large currents and support high voltages. Modern power devices are generally fabricated from monocrystalline silicon semiconductor material. One widely used power device is the power Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In a power MOSFET, a control signal is supplied to a gate electrode that is separated from the semiconductor surface by an intervening insulator, which may be, but is not limited to, silicon dioxide. Current conduction occurs via transport of majority carriers, without the presence of minority carrier injection that is used in bipolar transistor operation. Power MOSFETs can provide an excellent safe operating area, and can be paralleled in a unit cell structure.
As is well known to those having skill in the art, power MOSFETs may include a lateral structure or a vertical structure. In a lateral structure, the drain, gate and source terminals are on the same surface of a substrate. In contrast, in a vertical structure, the source and drain are on opposite surfaces of the substrate.
One widely used silicon power MOSFET is the double diffused MOSFET (DMOSFET) which is fabricated using a double-diffusion process. In these devices, a p-base region and an n+ source region are diffused through a common opening in a mask. The p-base region is driven in deeper than the n+ source. The difference in the lateral diffusion between the p-base and n+ source regions forms a surface channel region. An overview of power MOSFETs including DMOSFETs may be found in the textbook entitled xe2x80x9cPower Semiconductor Devicesxe2x80x9d by B. J. Baliga, published by PWS Publishing Company, 1996, and specifically in Chapter 7, entitled xe2x80x9cPower MOSFETxe2x80x9d, the disclosure of which is hereby incorporated herein by reference.
Recent development efforts in power devices have also included investigation of the use of silicon carbide (SiC) devices for power devices. Silicon carbide has a wide bandgap, a lower dielectric constant, a high breakdown field strength, a high thermal conductivity, and a high saturation electron drift velocity compared to silicon. These characteristics may allow silicon carbide power devices to operate at higher temperatures, higher power levels and with lower specific on-resistance than conventional silicon-based power devices. A theoretical analysis of the superiority of silicon carbide devices over silicon devices is found in a publication by Bhatnagar et al. entitled xe2x80x9cComparison of 6Hxe2x80x94SiC, 3Cxe2x80x94SiC and Si for Power Devicesxe2x80x9d, IEEE Transactions on Electron Devices, Vol. 40, 1993, pp. 645-655. A power MOSFET fabricated in silicon carbide is described in U.S. Pat. No. 5,506,421 to Palmour entitled xe2x80x9cPower MOSFET in Silicon Carbidexe2x80x9d and assigned to the assignee of the present invention.
Notwithstanding these potential advantages, it may be difficult to fabricate power devices including power MOSFETs in silicon carbide. For example, as described above, the double-diffused MOSFET (DMOSFET) is generally fabricated in silicon using a double diffusion process wherein the p-base region is driven in deeper than the n+ source. Unfortunately, in silicon carbide, the diffusion coefficients of conventional p- and n-type dopants are small compared to silicon, so that it may be difficult to obtain the required depths of the p-base and n+ source regions using acceptable diffusion times and temperatures. Ion implantation may also be used to implant the p-base and the n+ source. See, for example, xe2x80x9cHigh-Voltage Double-Implanted Power MOSFET""s in 6Hxe2x80x94SiCxe2x80x9d by Shenoy et al., IEEE Electron Device Letters, Vol. 18, No. 3, March 1997, pp. 93-95. However, it may be difficult to control the depth and lateral extent of ion implanted regions. Moreover, the need to form a surface channel surrounding the source region may require the use of two separate implantation masks. It may then be difficult to align the p-base and the source regions to one another, thereby potentially impacting the device performance.
Methods of forming FETs in silicon carbide utilizing p-type implantation have also been described by, for example, commonly assigned U.S. patent application Ser. No. 09/093,207 entitled xe2x80x9cSelf-Aligned Method of Fabricating Silicon Carbide Power Devices by Implantation and Lateral Diffusion,xe2x80x9d the disclosure of which is incorporated herein by reference as if set forth fully herein. Also, PCT International Publication No. WO98/02916 describes a method for producing a doped p-type channel region layer having on laterally opposite sides thereof doped n-type regions in a silicon carbide layer for producing a voltage-controlled semiconductor device. A masking layer is applied on top of a silicon carbide layer that is lightly n-doped. An aperture is etched in the masking layer extending to the silicon carbide layer. N-type dopants are implanted into an area of the silicon carbide layer defined by the aperture for obtaining a high doping concentration of n-type in the surface-near layer of the silicon carbide layer under the area. P-type dopants having a considerably higher diffusion rate in silicon carbide than the n-type dopants, are implanted into an area of the silicon carbide layer defined by the aperture to such a degree that the doping type of the surface-near layer is maintained. The silicon carbide layer is then heated at such a temperature that the p-type dopants implanted in the surface-near layer diffuse into the surrounding regions of the silicon carbide layer that is lightly n-doped, to such a degree that a channel region layer in which p-type dopants dominates is created laterally to the highly doped n-type surface-near layer and between this layer and lightly n-doped regions of the silicon carbide layer. As described in this International Application, the heating is carried out a temperature above 1650xc2x0 C. and below 1800xc2x0.
As the above illustrates, the difficulties of implantation and diffusion in silicon carbide may make the production of power devices such as the DMOSFET. Accordingly, improvements may be needed in manufacturing processes and device structures of silicon carbide devices such as silicon carbide DMOSFETs.
In first embodiments, the present invention provides methods of fabricating silicon carbide devices by forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide is formed extending through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer. At least one second region of n-type silicon carbide is also formed adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric is formed over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact is also formed so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide. A second contact is also formed on the substrate. Thus, a silicon carbide power device may be formed without the need for a p-type implant.
In particular embodiments of the present invention, the formation of at least one first region of n-type silicon carbide through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer and at least one second region of n-type silicon carbide which is adjacent and spaced apart from the first region of n-type silicon carbide is carried out by implanting n-type dopants in the p-type silicon carbide epitaxial layer. Furthermore, in an alternative embodiment of the present invention, the formation of at least one first region of n-type silicon carbide through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer may be preceded by etching a trench in the first p-type silicon carbide epitaxial layer. In such an embodiment, the n-type dopants may be implanted in exposed surfaces of the trench.
Preferably, the implantation of n-type dopants in the p-type silicon carbide epitaxial layer is followed by the activation of the implanted n-type dopants. Such activation may be accomplished by exposing the implanted first p-type epitaxial layer to a temperature of from about 900xc2x0 C. to about 1400xc2x0 C. Preferably, the n-type dopant is phosphorous. In such a case, it may be preferred that the activation of the phosphorous be carried out at a temperature of about 1200xc2x0 C. Such annealing temperatures may activate the implanted ions with less damage to the silicon carbide than higher temperatures.
In other embodiments of the present invention, exposed portions of the first p-type epitaxial layer are capped with a passivating material prior to activating the implanted n-type dopants. In a further embodiment, the gate dielectric may be formed by patterning the passivating material so as to provide the gate dielectric.
In still further embodiments of the present invention, a second p-type silicon carbide epitaxial layer is formed on the p-type silicon carbide epitaxial layer. The second p-type silicon carbide epitaxial layer preferably has a carrier concentration higher than the first p-type silicon carbide epitaxial layer. The second p-type silicon carbide epitaxial layer may then be patterned so as to provide a at least one p+ contact region, wherein the at least one p+ contact region is adjacent the at least one second n-type region and wherein the at least one second n-type region is between the at least one p+ contact region and the at least one first n-type region. In a further embodiment, the first contact is formed so as to contact the at least one p+ contact region and the at least one second region of n-type silicon carbide. Thus a high quality contact may be formed without requiring p-type implantation.
In yet other embodiments of the present invention, a voltage absorbing region is formed around the silicon carbide device. In particular embodiments, the voltage absorbing region is formed by etching the first p-type epitaxial layer so as to form at least one step having a sidewall which extends into the first p-type silicon carbide epitaxial layer and wherein the sidewall of the at least one step is spaced apart from the at least one second n-type region. In further embodiments the p-type epitaxial layer is etched to form a plurality of steps. Furthermore, n-type dopants may be implanted in the at least one step of the first p-type epitaxial layer to compensate p-type dopants in the first p-type epitaxial layer. Preferably, the n-type dopants are implanted at a distance from the sidewall of the step based on a desired breakdown voltage of the power device.
In particular embodiments of the present invention, the formation of the gate dielectric comprises forming an oxide layer over exposed portions of the first p-type epitaxial layer and the formation of the first contact comprises etching the oxide layer so as to form a first contact hole and depositing metal in the first contact hole.
In further embodiments of the present invention, a unit cell of a vertical silicon carbide power device includes a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide extends through the first p-type silicon carbide epitaxial layer to the n-type silicon carbide substrate so as to provide a channel region. At least one second region of n-type silicon carbide is adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric extends over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact contacts a portion of the p-type epitaxial layer and the second region of n-type silicon carbide and a second contact is formed on the substrate.
In further embodiments of the present invention, the first and second regions of n-type silicon carbide are regions of the first p-type epitaxial layer with implanted n-type dopants. In still further embodiments, a trench is formed in the first p-type epitaxial layer and wherein the channel region comprises a region of n-type silicon carbide adjacent sidewalls of the trench.
In still further embodiments, at least one p-type contact region of epitaxial p-type silicon carbide is formed on the first p-type epitaxial layer, wherein the at least one p-type contact region has a carrier concentration higher than the first p-type silicon carbide epitaxial layer so as to provide at least one p+ contact region. The at least one p+ contact region is adjacent the at least one second n-type region and the at least one second n-type region is between the at least one p+ contact region and the at least one first n-type region. In a further embodiment, the first contact contacts the at least one p+ contact region and the at least one second region of n-type silicon carbide.
In still other embodiments, the first p-type epitaxial layer is on an n-type epitaxial layer which is on the n-type substrate, wherein the n-type epitaxial layer has a carrier concentration which is less than that of the n-type substrate.
In other embodiments of the present invention, the first p-type epitaxial layer forms at least one step having a sidewall which extends into the first p-type silicon carbide epitaxial layer and wherein the sidewall of the at least one step is spaced apart from the at least one second n-type region. Furthermore, the first p-type epitaxial may also form a plurality of steps. A compensation region of n-type dopants may also be formed in the at least one step to compensate p-type dopants in the first p-type epitaxial layer. The compensation region may be a distance from the sidewall of the step corresponding to a desired breakdown voltage of the power device.
In still further embodiments of the present invention, a passivating layer is formed on exposed portions of the p+ contact regions and the first p-type epitaxial layer.